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ADC1213D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
Rev. 6 -- 9 February 2011 Product data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1213D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane is differential and complies with the JESD204A standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up. The device also includes a programmable full-scale SPI to allow flexible input voltage range of 1 V to 2 V (peak-to-peak). Excellent dynamic performance is maintained from the baseband to input frequencies of 170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and medical applications.
2. Features and benefits
SNR, 70 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps Clock input divided by 2 for less jitter contribution 3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) Two configurable serial outputs Compliant with JESD204A serial transmission standard Pin compatible with the ADC1613D series, ADC1413D series, and ADC1113D125 Input bandwidth, 600 MHz Power dissipation, 995 mW at 80 Msps SPI register programming Duty cycle stabilizer (DCS) High IF capability Offset binary, two's complement, gray code Power-down mode and Sleep mode HVQFN56 package
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
3. Applications
Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio
4. Ordering information
Table 1. Ordering information Sampling frequency (Msps) 125 105 80 65 Package Name HVQFN56 HVQFN56 HVQFN56 HVQFN56 Description Version Type number
ADC1213D125HN/C1 ADC1213D105HN/C1 ADC1213D080HN/C1 ADC1213D065HN/C1
plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 8 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 8 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 8 0.85 mm plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 8 0.85 mm
ADC1213D_SER
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Product data sheet
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
5. Block diagram
CFG (0 to 3) SCLK SDIO CS
ERROR CORRECTION AND DIGITAL PROCESSING
SPI
SYNCP SYNCN
INAP T/H INPUT STAGE INAM 8-bit CLOCK INPUT STAGE & DUTY CYCLE CONTROL FRAME ASSEMBLY ADC A CORE 12-BIT PIPELINED D11 to D0 OTR SCRAMBLER A ENCODER 8-bit/10-bit A
SWING_n
SERIALIZER A 10-bit OUTPUT BUFFER A
CMLPA
8-bit
CMLNA
CLKP DLL PLL CLKM ERROR CORRECTION AND DIGITAL PROCESSING
ENCODER 8-bit/10-bit B
SCRAMBLER B
SERIALIZER B 10-bit OUTPUT BUFFER B
CMLPB
8-bit
8-bit
INBP T/H INPUT STAGE INBM ADC B CORE 12-BIT PIPELINED
OTR D11 to D0
CMLNB
SWING_n
CLOCK INPUT STAGE & DUTY CYCLE CONTROL
SYSTEM REFERENCE AND POWER MANAGEMENT
ADC1213D
SCRAMBLER RESET REFBT REFBB VCMB REFAB REFAT VCMA
005aaa120
SENSE VREF
Fig 1.
Block diagram
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
48 SWING_1 47 SWING_0
44 SYNCN
INAP INAM VCMA REFAT REFAB AGND CLKP CLKN AGND
1 2 3 4 5 6 7 8 9
43 SYNCP 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND 35 DGND 34 VDDD 33 CMLNB 32 CMLPB 31 VDDD 30 DGND 29 DGND DGND 28
005aaa121
54 SENSE
ADC1213D
REFBB 10 REFBT 11 VCMB 12 INBM 13 INBP 14 VDDA 15 VDDA 16 SCLK 17 SDIO 18 CS 19 AGND 20 RESET 21 SCRAMBLER 22 CFG0 23 CFG1 24 CFG2 25 CFG3 26 VDDD 27
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB
ADC1213D_SER
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 Type [1] I I O O O G I I G O O O Description channel A analog input channel A complementary analog input channel A output common voltage channel A top reference channel A bottom reference analog ground clock input complementary clock input analog ground channel B bottom reference channel B top reference channel B output common voltage
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Product data sheet
Rev. 6 -- 9 February 2011
45 DGND
52 AGND
51 AGND
46 VDDD
56 VDDA
53 VDDA
50 VDDA
55 VREF
49 DNC
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Pin description ...continued Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Type [1] I I P P I I/O I G I I I/O I/O I/O I/O P G G G P O O P G G P O O P G G I I G P I I O P G G Description channel B complementary analog input channel B analog input analog power supply 3 V analog power supply 3 V SPI clock SPI data input/output chip select analog ground JEDEC digital IP reset scrambler enable and disable see Table 28 (input) or OTRA (output)[2] see Table 28 (input) or OTRB (output)[2] see Table 28 (input) see Table 28 (input) digital power supply 1.8 V digital ground digital ground digital ground digital power supply 1.8 V channel B output channel B complementary output digital power supply 1.8 V digital ground digital ground digital power supply 1.8 V channel A complementary output channel A output digital power supply 1.8 V digital ground digital ground synchronization from FPGA synchronization from FPGA digital ground digital power supply 1.8 V JESD204 serial buffer programmable output swing JESD204 serial buffer programmable output swing do not connect analog power supply 3 V analog ground analog ground
Table 2. Symbol INBM INBP VDDA VDDA SCLK SDIO CS AGND RESET
SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 DNC VDDA AGND AGND
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Pin description ...continued Pin 53 54 55 56 Type [1] P I I/O P Description analog power supply 3 V reference programming pin voltage reference input/output analog power supply 3 V
Table 2. Symbol VDDA SENSE VREF VDDA
[1] [2]
P: power supply; G: ground; I: input; O: output; I/O: input/output. OTRA stands for "OuT of Range" A. OTRB stands for "OuT of Range" B
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD Tstg Tamb Tj Parameter analog supply voltage digital supply voltage storage temperature ambient temperature junction temperature Conditions Min 0.4 0.4 55 40 Max +4.6 +2.5 +125 +85 125 Unit V V C C C
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 17.8 6.8
Unit K/W K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 5. Symbol Supplies VDDA VDDD IDDA IDDD Ptot analog supply voltage digital supply voltage analog supply current digital supply current total power dissipation fclk = 125 Msps; fi = 70 MHz fclk = 125 Msps; fi = 70 MHz fclk = 125 Msps fclk = 105 Msps fclk = 80 Msps fclk = 65 Msps 2.85 1.65 3.0 1.8 343 150 1270 1150 995 885 3.4 1.95 V V mA mA mW mW mW mW Static characteristics[1] Parameter Conditions Min Typ Max Unit
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 5. Symbol P
Static characteristics[1] ...continued Parameter power dissipation Conditions Power-down mode Standby mode Min Typ 30 200 Max Unit mW mW
Clock inputs: pins CLKP and CLKM (AC-coupled) Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Vi(clk)dif SINE Vi(clk)dif differential clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current peak-to-peak track mode track mode track mode track mode peak-to-peak 0.8 1.5 V differential clock input voltage peak-to-peak 0.8 V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) VIL VIH VIL VIH IIL IIH VIL VIH IIL IIH CI II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) 0.7VDDA 6 30 0 0.7VDDA 10 50 5 0.9 1 0 0.66VDDD 4 15 5 1.5 600 VDDA / 2 4 0.3VDDA +6 +30 0.3VDDA VDDA +10 +50 +5 2 2 V V V V A A V V A A pF A pF V MHz V V mA
Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESET
SPI: pins CS, SDIO, and SCLK
Analog inputs: pins INAP, INAM, INBP, and INBM
Voltage controlled regulator output: pins VCMA and VCMB
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 5. Symbol VVREF
Static characteristics[1] ...continued Parameter voltage on pin VREF Conditions output input Min 0.5 0.5 Typ pin AGND; VVREF; VDDA Max 1 1 Unit V V V
Reference voltage input/output: pin VREF
Reference mode selection: pin SENSE VSENSE voltage on pin SENSE
Data outputs: pins CMLPA, CMLNA Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000 VOL VOH LOW-level output voltage HIGH-level output voltage DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled DC coupled; output AC coupled differential; input 5 guaranteed no missing codes full-scale 0.95 1.5 1.35 1.8 1.65 1.45 1.275 1.8 1.625 1.4 1.2 1.8 1.6 1.35 1.125 1.8 1.575 1.3 1.05 1.8 1.55 0.95 1.47 0.5 2 0.5 +5 +0.95 V V V V V V V V V V V V V V V V V V V V V V LSB LSB mV %
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Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001 VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010 VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011 VOL VOH LOW-level output voltage HIGH-level output voltage
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100 VOL VOH LOW-level output voltage HIGH-level output voltage
Serial configuration: pins SYNCCP, SYNCCN VIL VIH Accuracy INL DNL Eoffset EG
ADC1213D_SER
LOW-level input voltage
HIGH-level input voltage differential; input integral non-linearity differential non-linearity offset error gain error
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 5. Symbol MG(CTC) Supply PSRR
Static characteristics[1] ...continued Parameter channel-to-channel gain matching power supply rejection ratio 200 mV (p-p) on pin VDDA; fi = DC Conditions Min Typ 1.1 Max Unit %
-
54
-
dB
[1]
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
ADC1213D_SER
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Product data sheet
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10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6. Symbol Dynamic characteristics[1] Parameter Conditions ADC1213D065 Min Analog signal processing 2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-to-noise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 87 86 85 82 86 85 84 81 83 82 81 78 11.3 11.3 11.2 11.1 70.0 69.5 69.2 68.8 86 85 84 81 87 86 85 82 86 85 84 81 83 82 81 78 11.3 11.3 11.2 11.1 69.9 69.5 69.2 68.8 86 85 84 81 86 86 84 81 85 85 83 80 82 82 80 77 11.3 11.3 11.2 11.1 69.8 69.5 69.1 68.7 85 85 83 80 88 87 85 83 87 86 84 82 84 83 81 79 11.3 11.2 11.2 11.1 69.6 69.4 69.0 68.6 87 86 84 82 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc Typ Max ADC1213D080 Min Typ Max ADC1213D105 Min Typ Max ADC1213D125 Min Typ Max Unit
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Dual 12-bit ADC; serial JESD204A interface
ADC1213D series
SFDR
spurious-free dynamic range
fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz
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Table 6. Symbol IMD Dynamic characteristics[1] ...continued Parameter Conditions ADC1213D065 Min intermodulation distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ct(ch)
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ADC1213D080 Min Typ 89 88 87 85 100 Max -
ADC1213D105 Min Typ 88 88 86 83 100 Max -
ADC1213D125 Min Typ 89 88 86 84 100 Max -
Unit dBc dBc dBc dBc dBc
Typ 89 88 87 84 100
Max
channel crosstalk
fi = 70 MHz
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
Table 7. Clock and digital output characteristics[1] Conditions ADC1213D065 Min Clock timing input: pins CLKP and CLKM fclk tlat(data) clk td(s) twake
[1]
Symbol Parameter
ADC1213D080 Min 60 250 30 45 Typ 50 50 0.8 76 Max 80 283 70 55 -
ADC1213D105 Min 75 190 30 45 Typ 50 50 0.8 76 Max 105 226 70 55 -
ADC1213D125 Min 100 160 30 45 Typ 50 50 0.8 76 Max 125 170 70 55 -
Unit
Typ 50 50 0.8 76
Max 65 850 70 55 -
clock frequency data latency time clock duty cycle sampling delay time wake-up time clock cycles DCS_EN = logic 1 DCS_EN = logic 0
40 307 30 45 -
Msps ns % % ns s
Dual 12-bit ADC; serial JESD204A interface
ADC1213D series
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions are:
* 3.125 Gbps data rate * Tamb = 25 C * DC coupling with two different receiver common-mode voltages
005aaa088
Fig 3.
Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4.
Eye diagram at 2 V receiver common-mode
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
10.4 SPI timing
Table 8. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max)
[1]
SPI timing characteristics [1] Parameter SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLK H CS to SCLK H data to SCLK H CS to SCLK H Conditions Min Typ 40 16 16 5 5 2 2 25 Max Unit ns ns ns ns ns ns ns MHz
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM,INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
tsu CS
tsu th
tw(SCLKL) tw(SCLK) tw(SCLKH)
th
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 5.
SPI timing
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1213D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.2 and Table 21). Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
package
ESD
parasitics
switch INAP INBP 1, 14
Ron = 15 4 pF Cs
internal clock
INAM INBM
2, 13
Ron = 15
switch
4 pF Cs
internal clock
005aaa069
Fig 6.
Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a charge injection generated by the sampling capacitance. The RC filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively.
R
INPA/ INBP
C
R
INAM/ INBM
001aan679
Fig 7.
Anti-kickback circuit
The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth.
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
RC coupling versus input frequency - typical values Resistance () 25 12 12 Capacitance (pF) 12 8 8 3 70 170
Table 9.
Input frequency (MHz)
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 8 would be suitable for a baseband application.
100 nF
Analog input
100 nF
ADT1-1WT
25
25
INAP INBP
12 pF
100 nF 100 nF
25
25
INAM INBM VCM
100 nF
100 nF
005aaa070
Fig 8.
Single transformer configuration
ADT1-1WT
100 nF 50
ADT1-1WT
50
12
INAP INBP
8.2 pF
Analog input
50
50
12
100 nF
INAM INBM VCM
100 nF
100 nF
005aaa071
Fig 9.
Dual transformer configuration
The configuration shown in Figure 9 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance.
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent reference circuit is shown in Figure 10. An external reference is also possible by providing a voltage on pin VREF as described in Figure 13.
REFAT/ REFBT REFERENCE AMP REFAB/ REFBB
VREF
EXT_ref
BUFFER
EXT_ref
BANDGAP REFERENCE
ADC CORE SENSE SELECTION LOGIC
001aan670
Fig 10. Reference equivalent schematic
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 10.
Table 10. Mode Internal (Figure 11) Internal (Figure 12) External (Figure 13) Internal, SPI mode (Figure 14) Reference modes SPI bit, "Internal reference" 0 0 0 1 SENSE pin GND VREF pin Full-scale (V (p-p))
330 pF capacitor 2 to GND 1
VREF pin = SENSE pin and 330 pF capacitor to GND VDDA
external voltage 1 to 2 from 0.5 V to 1 V 1 to 2
VREF pin = SENSE pin and 330 pF capacitor to GND
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source.
VREF
330 pF
VREF
330 pF
REFERENCE EQUIVALENT SCHEMATIC
REFERENCE EQUIVALENT SCHEMATIC SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
0.1 F
VREF
V
330 pF
REFERENCE EQUIVALENT SCHEMATIC SENSE
REFERENCE EQUIVALENT SCHEMATIC
SENSE
VDDA
005aaa119
005aaa118
Fig 13. External reference, 1 V (p-p) to 2 V (p-p) full-scale
Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Table 11. 000 001 010 011 100 101 110 111 Programmable full-scale Level (dB) 0 1 2 3 4 5 6 not used Full-scale (V (p-p)) 2 1.78 1.59 1.42 1.26 1.12 1 x
INTREF[2:0]
11.2.3 Common-mode output voltage (VO(cm))
An 0.1 F filter capacitor should be connected between the pins VCMA and VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point.
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
PACKAGE
ESD
PARASITICS COMMON MODE REFERENCE
1.5 V VCMA VCMB
0.1 F
ADC CORE
005aaa077
Fig 15. Reference equivalent schematic
11.2.4 Biasing
The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage (pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1213D can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor).
LVCMOS clock input
CLKP CLKP CLKM LVCMOS clock input CLKM
005aaa174
005aaa053
a. Rising edge LVCMOS Fig 16. LVCMOS single-ended clock input
b. Falling edge LVCMOS
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
CLKP Sine clock input
Sine clock input
CLKP
CLKM
CLKM
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP LVPECL clock input
CLKM
005aaa172
c. LVPECL clock input Fig 17. Differential clock input
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via 5 k internal resistors.
package
ESD
parasitics
CLKP
Vcm(clk) SE_SEL SE_SEL
5 k
5 k
CLKM
005aaa081
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor.
11.3.3 Clock input divider
The ADC1413D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed.
11.3.4 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by compensating the input clock signal duty cycle. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %.
Table 12. 0 1 Duty cycle stabilizer Description duty cycle stabilizer disable duty cycle stabilizer enable
Bit DCS_EN
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled, both must be fed from the same supply.
VDDD
50
CMLPA/CLMPB
100
RECEIVER
CMLNA/CLMNB + -
12 mA to 26 mA
AGND
005aaa082
Fig 19. CML output connection to the receiver (DC-coupled)
The output should be terminated when 100 (typical) is reached at the receiver side.
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VDDD
50
CMLPA/CMLPB
10 nF
CMLNA/CMLNB
10 nF
100
RECEIVER
+
-
12 mA to 26 mA
005aaa083
Fig 20. CML output connection to the receiver (AC-coupled)
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side. The block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
N bits from Cr0 + CS bits for control
F octets TX transport layer
FRAME TO OCTETS
SCRAMBLER
ALIGNMENT CHARACTER GENERATOR
8-bit/ 10-bit
SER
LANE 0
SYNC~
TX CONTROLLER
N bits from CrM-1 + CS bits for control
samples stream to lane stream mapping
F octets
FRAME TO OCTETS
SCRAMBLER
ALIGNMENT CHARACTER GENERATOR
8-bit/ 10-bit
SER
LANE 1
N' = N+CS S samples per frame cycle
CF: position of control bits HD: frame boundary break Padding with Tail bits (TT) Lx(F) octets L octets
005aaa084
Mx(N'xS) bits
Fig 21. General overview of the JESD204A serializer
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
ADC_MODE[1:0] SCR_IN_MODE[1:0] N 12 + 1 AND CS LANE_MODE[1:0] N + CS 8 00 SCR PRBS 01 8-bit/ 10-bit '0' ADC A 12 + 1 00 '0/1' PRBS 10 10 00
PRBS
11
DUMMY
12 + 1
10
ADC_PD
LANE_POL SER
01
x1 PLL AND DLL xF x 10F
frame CLK character CLK bit CLK FRAME ASSEMBLY
FSM (frame assembly character replication ILA test mode)
11
SWING_SEL[2:0] 11
PRBS
'0/1' ADC B 12 + 1 00 '0' ADC_PD PRBS N 12 + 1 AND CS 01 SCR N + CS 8 00 8-bit/ 10-bit 10
10
SER
01 LANE_POL 00
DUMMY PRBS
12 + 1 10
LANE_MODE[1:0] SCR_IN_MODE[1:0] sync_request
005aaa175
11
ADC_MODE[1:0]
Fig 22. Detailed view of the JESD204A serializer with debug functionality
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. < 1 1.0000000 0.9995117 0.9990234 0.9985352 0.9980469 .... 0.0009766 0.0004883 0.0000000 +0.0004883 +0.0009766 .... +0.9980469 Output codes versus input voltage Offset binary 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0010 0000 0000 0011 0000 0000 0100 .... 0111 1111 1110 0111 1111 1111 1000 0000 0000 1000 0000 0001 1000 0000 0010 .... 1111 1111 1011 Two's complement 1000 0000 0000 1000 0000 0000 1000 0000 0001 1000 0000 0010 1000 0000 0011 1000 0000 0100 .... 1111 1111 1110 1111 1111 1111 0000 0000 0000 0000 0000 0001 0000 0000 0010 .... 0111 1111 1011 OTR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 INP INM (V)
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Output codes versus input voltage ...continued Offset binary 1111 1111 1100 1111 1111 1101 1111 1111 1110 1111 1111 1111 1111 1111 1111 Two's complement 0111 1111 1100 0111 1111 1101 0111 1111 1110 0111 1111 1111 0111 1111 1111 OTR 0 0 0 0 1
Table 13.
INP INM (V) +0.9985352 +0.9990234 +0.9995117 +1.0000000 > +1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. This interface is configured as a 3-wire type (SDIO as bidirectional pin). SCLK acts as the serial clock, and CS acts as the serial chip select. Each read/write operation is sequenced by the CS signal and enabled by a LOW level to to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see Table 14).
Table 14. Bit Description SPI instruction bytes MSB 7 R/W[1] A7
[1]
LSB 6 W1 A6 5 W0 A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0
R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte
Table 15. R/W[1] 0 1
[1]
Read or Write mode access description Description Write mode operation Read mode operation
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16. W1 0 0 1 1
Number of bytes to be transferred W0 0 1 0 1 Number of bytes transferred 1 byte 2 bytes 3 bytes 4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incremented to access subsequent addresses.
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Dual 12-bit ADC; serial JESD204A interface
The steps for a data transfer: 1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes) 4. A rising edge on pin CS indicates the end of data transmission.
CS
SCLK
SDIO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
11.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the register "Channel index", the user can choose which ADC channel receives the next SPI-instruction. By default the channel A and B receives the same instructions in write mode. In read mode only A is active.
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Table 17.
Register allocation map Access[1] Bit 7 R/W R/W SW_ RST Bit 6 Bit 5 Bit 4 Bit definition Bit 3 Bit 2 Bit 1 ADCB PD[1:0] Bit 0 ADCA Default (bin)
Address Register name (hex) ADC control register 0003 0005 Channel index Reset and Power-down modes Clock Vref Offset Test pattern 1 Test pattern 2 Test pattern 3 Ser_Status Ser_Reset Ser_Cfg_Setup Ser_Control1
1111 1111 0000 0000
0006 0008 0013 0014 0015 0016 0801 0802 0803 0805
R/W R/W R/W R/W R/W R/W R R/W R/W R/W
-
-
SE_SEL -
DIFF_SE INTREF_ EN
-
CLKDIV2_ SEL INTREF[2:0]
DCS_EN
0000 0001 0000 0000 0000 0000
DIG_OFFSET[5:0] TESTPAT_2[11:4] 0 0 0 SYNC_ SINGLE_ ENDED 0 0 1 FSM_SW_ RST 0 0 TESTPAT_1[2:0] POR_TST 0 CFG_SETUP[3:0] REV_ SCR 0 REV_ ENCODER SWAP_ LANE_0_1 REV_ SERIAL SWAP_ ADC_A_B RESERVED 0
0000 0000 0000 0000 0000 0000 0010 0000 0000 0000
TESTPAT_3[3:0] RXSYNC _ERROR SW_ RST 0 0 0 0 TRISTATE_ CFG_PINS 0 0 RESERVED[2:0] 0 0 SYNC_ POL 0 0
JESD204A control
Dual 12-bit ADC; serial JESD204A interface
0000 1000 0100 1001
ADC1213D series
0806 0808 0809 080A 080B 0820 0821 0822 0823
Ser_Control2 Ser_Analog_Ctrl Ser_ScramblerA Ser_ScramblerB Ser_PRBS_Ctrl Cfg_0_DID Cfg_1_BID Cfg_3_SCR_L Cfg_4_F
R/W R/W R/W R/W R/W R* R/W* R/W* R/W*
0 0 0 0 0 SCR 0
0 0 LSB_INIT[6:0] MSB_INIT[7:0]
0000 0011 0000 0011 0000 0000 1111 1111
SWING_SEL[2:0]
0 0 0 0
0 0 0 0
0 0 0 0
0 DID[7:0]
0
PRBS_TYPE[1:0] BID[3:0]
0000 0000 1110 1101 0000 1010
0 0
0
0 F[2:0]
L
0000 0000 0000 0001
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map ...continued Access[1] Bit 7 R/W* R/W* R/W* R/W R/W* R/W* R/W* R/W* R R R/W R/W R/W R/W 0 0 0 0 SCR_IN_ MODE SCR_IN_ MODE 0 0 LANE_MODE[1:0] LANE_MODE[1:0] ADC_MODE[1:0] ADC_MODE[1:0] 0 0 0 0 0 HD 0 0 Bit 6 0 0 CS[0] 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 FCHK[7:0] FCHK[7:0] 0 0 0 0 LANE_ POL LANE_ POL 0 0 LANE_CLK_ POS_EDGE LANE_CLK_ POS_EDGE 0 0 LANE_PD LANE_PD ADC_PD ADC_PD 0 0 0 0 0 0 NP[4:0] 0 0 LID[4:0] LID[4:0] 0 CF[1:0] S 0 Bit 4 Bit definition Bit 3 Bit 2 K[4:0] 0 0 N[3:0] M Bit 1 Bit 0 Default (bin) 0000 1000 0000 0000 0100 0010 0000 1111 0000 0000 0000 0000 0001 1011 0001 1100 0000 0000 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000
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Address Register name (hex) 0824 0825 0826 0827 0828 0829 082C 082D 084C 084D 0870 0871 0890 0891
[1]
Cfg_5_K Cfg_6_M Cfg_7_CS_N Cfg_8_Np Cfg_9_S Cfg_10_HD_CF Cfg_01_2_LID Cfg_02_2_LID Cfg01_13_FCHK Cfg02_13_FCHK Lane0_0_Ctrl Lane1_0_Ctrl ADCA_0_Ctrl ADCB_0_Ctrl
an "*" in the Access column means that this register is subject to control access conditions in Write mode.
Dual 12-bit ADC; serial JESD204A interface
ADC1213D series
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control register
Table 18. Register Channel index (address 0003h) Default values are highlighted. Bit 7 to 2 1 Symbol not used ADCB Access R/W 0 1 0 ADCA R/W 0 1 Value 111111 Description not used ADC B gets the next SPI command: ADC B not selected ADC B selected ADC A gets the next SPI command: ADC A not selected ADC A selected
Table 19. Register Reset and Power-down mode (address 0005h) Default values are highlighted. Bit 7 Symbol SW_RST Access R/W 0 1 6 to 4 3 to 2 1 to 0 RESERVED[2:0] PD[1:0] R/W 00 01 10 11 Table 20. Register Clock (address 0006h) Default values are highlighted. Bit 7 to 5 4 Symbol SE_SEL Access R/W 0 1 3 DIFF_SE R/W 0 1 2 1 CLKDIV2_SEL R/W 0 1 0 Value 000 Description not used select SE clock input pin: select CLKM input select CLKP input differential/single-ended clock input select: fully differential single-ended not used select clock input divider by 2: disable active 000 00 Value Description reset digital part: no reset performs a reset of the digital part reserved not used Power-down mode: normal (power-up) full power-down sleep normal (power-up)
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Table 20. Register Clock (address 0006h) ...continued Default values are highlighted. Bit 0 Symbol DCS_EN Access R/W 0 1 Table 21. Register Vref (address 0008h) Default values are highlighted. Bit 7 to 4 3 Symbol INTREF_EN Access R/W 0 1 2 to 0 INTREF[2:0] R/W 000 001 010 011 100 101 110 111 Value 0000 Description not used enable internal programmable VREF mode: disable active programmable internal reference: 0 dB (FS=2 V) 1 dB (FS=1.78 V) 2 dB (FS=1.59 V) 3 dB (FS=1.42 V) 4 dB (FS=1.26 V) 5 dB (FS=1.12 V) 6 dB (FS=1 V) not used Value Description duty cycle stabilizer enable: disable active
Table 22. Digital offset adjustment (address 0013h) Default values are highlighted. Register offset: Decimal +31 ... 0 ... 32 DIG_OFFSET[5:0] 011111 ... 000000 ... 100000 +31 LSB ... 0 ... 32 LSB
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Table 23. Register Test pattern 1 (address 0014h) Default values are highlighted. Bit 7 to 3 2 to 0 Symbol TESTPAT_1[2:0] Access R/W 000 001 010 011 100 101 110 111 Table 24. Register Test pattern 2 (address 0015h) Default values are highlighted. Bit 7 to 0 Symbol TESTPAT_2[11:4] Access R/W Value Description 00000000 custom digital test pattern (bit 11 to 4) Value 00000 Description not used digital test pattern: off mid-scale FS + FS toggle `1111..1111'/'0000..0000' custom test pattern, to be written in register 0015h and 0016h `010101...' `101010...'
Table 25. Register Test pattern 3 (address 0016h) Default values are highlighted. Bit 7 to 4 3 to 0 Symbol TESTPAT_3[3:0] Access R/W Value 0000 0000 Description custom digital test pattern (bit 3 to 0) not used
11.6.4 JESD204A digital control registers
Table 26. Ser_Status (address 0801h) Default values are highlighted. Bit 7 6 to 4 3 to 2 1 0 Symbol RXSYNC_ERROR RESERVED[2:0] POR_TST RESERVED Access R R Value 0 010 0 1 Description set to 1 when a synchronization error occurs reserved not used power-on-reset reserved
Table 27. Ser_Reset (address 0802h) Default values are highlighted. Bit 7 6 to 4 3 2 to 0 Symbol SW_RST FSM_SW_RST Access R/W R/W Value 0 000 0 000 Description initiates a software reset of the JESD204Aunit not used initiates a software reset of the internal state machine of JESD204A unit not used
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Table 28. Ser_Cfg_Setup (address 0803h) Default values are highlighted. Bit Symbol Access Value R/W 0000 Description not used quick configuration of JESD204A. These settings overrule the CFG_PAD configuration (see Table 29). 7 to 4 3 to 0 CFG_SETUP[3:0]
Table 29. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
JESD204A configuration table Lane 1 ON OFF ON ON ON OFF ON OFF ON F[1] HD[1] K[1] M[1] L[1] 2 4 4 1 1 2 2 2 2 0 0 0 1 1 0 0 0 0 9 5 5 17 17 9 9 9 9 reserved reserved reserved reserved reserved ON OFF ON OFF ON OFF ON OFF 2 2 0 0 9 9 2 2 2 2 test: loop alignment chip power-down 1 1 0 0 1 1 2 2 2 1 1 1 1 1 1 2 1 1 2 2 1 1 1 1 Comment (F K) 17 (F K) 17 (F K) 17 (F K) 17 (F K) 17 (F K) 17 (F K) 17 (F K) 17 (F K) 17 CS[1] CF[1] S[1] 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ON ON ON ON OFF ON ON OFF OFF ON ON ON OFF ON OFF OFF ON ON ON ON OFF ON ON ON OFF ON OFF
CFG_SETUP[3:0] ADC A ADC B Lane 0
[1]
F: Octets per frame clock cycle HD: High-density mode K: Frame per multi-frame M: Converters per device L: Lane per converter device CS: Number of control bits per conversion sample CF: Control words per frame clock cycle and link S: Number of samples transmitted per single converter per frame cycle
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit 7 6 5 Symbol TRISTATE_CFG_PINS SYNC_POL Access R/W R/W 0 1 4 SYNC_SINGLE_ENDED R/W 0 1 3 2 REV_SCR 0 1 1 REV_ENCODER 0 1 0 REV_SERIAL 0 1 Table 31. Ser_Control2 (address 0806h) Default values are highlighted. Bit 7 to 2 1 Symbol SWAP_LANE_1_2 Access R/W 0 1 0 SWAP_ADC_0_1 R/W 0 1 Table 32. Ser_Analog_Ctrl (address 0808h) Default values are highlighted. Bit 7 to 3 2 to 0 Symbol SWING_SEL[2:0] Access R/W Value 00000 011 Description not used defines the swing output for the lane pads Value 000000 Description not used swaps the outputs of the JESD204A unit (output buffer A is connected to Lane 1, output buffer B is connected to Lane 0): disable enable swaps the inputs of the JESD204A unit (ADC A output is connected to ADC input B, ADC B is connected to ADC input A): disable enable 1 Value 0 1 Description not used pins CFG3 to CFG0 are set to high-impedance. Switch to 0 automatically after start-up or reset. defines the sync signal polarity: synchronization signal is active LOW synchronization signal is active HIGH defines the input mode of the sync signal: synchronization input mode is set in Differential mode synchronization input mode is set in Single-ended mode not used LSBs are swapped with MSBs at the scrambler input: disable enable LSBs are swapped with MSBs at the 8-bit/10-bit encoder input: disable enable LSBs are swapped with MSBs at the lane input: disable enable
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Table 33. Ser_ScramblerA (address 0809h) Default values are highlighted. Bit 7 6 to 0 Symbol LSB_INIT[6:0] Access R/W Value 0 0000000 Description not used defines the initialization vector for the scrambler polynomial (lower)
Table 34. Ser_ScramblerB (address 080Ah) Default values are highlighted. Bit 7 to 0 Symbol MSB_INIT[7:0] Access R/W Value 11111111 Description defines the initialization vector for the scrambler polynomial (upper)
Table 35. Ser_PRBS_Ctrl (address 080Bh) Default values are highlighted. Bit 7 to 2 1 to 0 Symbol PRBS_TYPE[1:0] Access R/W 00 (reset) 01 10 11 Table 36. Cfg_0_DID (address 0820h) Default values are highlighted. Bit 7 to 0 Symbol DID[7:0] Access R Value Description 11101101 defines the device (= link) identification number Value 000000 Description not used defines the type of Pseudo-Random Binary Sequence (PRBS) generator to be used: PRBS-7 PRBS-7 PRBS-23 PRBS-31
Table 37. Cfg_1_BID (address 0821h) Default values are highlighted. Bit 7 to 4 3 to 0 Symbol BID[3:0] Access R/W Value 0000 1010 Description not used defines the bank ID - extension to DID
Table 38. Cfg_3_SCR_L (address 0822h) Default values are highlighted. Bit 7 6 to 1 0 Symbol SCR L Access R/W R/W Value 0 000000 0 Description scrambling enabled not used defines the number of lanes per converter device, minus 1
Table 39. Cfg_4_F (address 0823h) Default values are highlighted. Bit 7 to 3 2 to 0 Symbol F[2:0] Access R/W Value 00000 001 Description not used defines the number of octets per frame, minus 1
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Table 40. Cfg_5_K (address 0824h) Default values are highlighted. Bit 7 to 5 4 to 0 Symbol K[4:0] Access R/W Value 000 01000 Description not used defines the number of frames per multiframe, minus 1
Table 41. Cfg_6_M (address 0825h) Default values are highlighted. Bit 7 to 1 0 Symbol M Access R/W Value 0000000 0 Description not used defines the number of converters per device, minus 1
Table 42. Cfg_7_CS_N (address 0826h) Default values are highlighted. Bit 7 6 5 to 4 3 to 0 Symbol CS[0] N[3:0] Access R/W R/W Value 0 1 00 0010 Description not used defines the number of control bits per sample, minus 1 not used defines the converter resolution
Table 43. Cfg_8_Np (address 0827h) Default values are highlighted. Bit 7 to 5 4 to 0 Symbol NP[4:0] Access R/W Value 000 01111 Description not used defines the total number of bits per sample, minus 1
Table 44. Cfg_9_S (address 0828h) Default values are highlighted. Bit 7 to 1 0 Symbol S Access R/W Value 0000000 0 Description not used defines number of samples per converter per frame cycle
Table 45. Cfg_10_HD_CF (address 0829h) Default values are highlighted. Bit 7 6 to 2 1 to 0 Symbol HD CF[1:0] Access R/W R/W Value 0 00000 00 Description defines high density format not used defines number of control words per frame clock cycle per link
Table 46. Cfg_01_2_LID (address 082Ch) Default values are highlighted. Bit 7 to 5 4 to 0 Symbol LID[4:0] Access R/W Value 000 11011 Description not used defines lane 0 identification number
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Dual 12-bit ADC; serial JESD204A interface
Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit 7 to 5 4 to 0 Symbol LID[4:0] Access R/W Value 000 11100 Description not used defines lane 1 identification number
Table 48. Cfg01_13_FCHK (address 084Ch) Default values are highlighted. Bit 7 to 0 Symbol FCHK[7:0] Access R Value Description checksum corresponds to the sum of all the link configuration parameters modulo 256 (as defined in JEDEC Standard No.204A) Table 49. Cfg02_13_FCHK (address 084Dh) Default values are highlighted. Bit 7 to 0 Symbol FCHK[7:0] Access R Value Description checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in JEDEC Standard No.204A) Table 50. Lane0_0_Ctrl (address 0870h) Default values are highlighted. Bit 7 6 Symbol SCR_IN_MODE Access R/W 0 (reset) 1 Value 0 Description not used defines the input type for scrambler and 8-bit/10-bit units: (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. input of the scrambler and 8-bit/10-bit units is the PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_Ctrl register) defines output type of lane output unit: 00 (reset) 01 10 11 3 2 LANE_POL R/W 0 1 1 LANE_CLK_POS_EDGE R/W 0 1 0 normal mode: lane output is the 8-bit/10-bit output unit constant mode: lane output is set to a constant (0 0) toggle mode: lane output is toggling between 0 0 and 0 1 PRBS mode: lane output is the PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_Ctrl register) not used defines lane polarity: lane polarity is normal lane polarity is inverted defines lane clock polarity: lane clock provided to the serializer is active on positive edge lane clock provided to the serializer is active on negative edge 00000000 defines the checksum value for lane 1 00000000 defines the checksum value for lane 0
5 to 4
LANE_MODE[1:0]
R/W
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 50. Lane0_0_Ctrl (address 0870h) ...continued Default values are highlighted. Bit 0 Symbol LANE_PD Access R/W 0 1 Table 51. Lane1_0_Ctrl (address 0871h) Default values are highlighted. Bit 7 6 Symbol SCR_IN_MODE Access R/W 0 (reset) 1 Value 0 Description not used defines the input type for scrambler and 8-bit/10-bit units: (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. input of the scrambler and 8-bit/10-bit units is the PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_Ctrl register) defines output type of lane output unit: 00 (reset) 01 10 11 3 2 LANE_POL R/W 0 1 1 LANE_CLK_POS_EDGE R/W 0 1 0 LANE_PD R/W 0 1 Table 52. ADCA_0_Ctrl (address 0890h) Default values are highlighted. Bit 7 to 6 5 to 4 Symbol ADC_MODE[1:0] R/W 00 (reset) 01 10 11 Access Value 00 Description not used defines input type of JESD204A unit: ADC output is connected to the JESD204A input not used JESD204A input is fed with a dummy constant, set to: OTR = 0 and ADC[11:0] = "100110111010" JESD204A is fed with a PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_Ctrl register)
(c) NXP B.V. 2011. All rights reserved.
Value
Description lane power-down control: lane is operational lane is in Power-down mode
5 to 4
LANE_MODE[1:0]
R/W
normal mode: lane output is the 8-bit/10-bit output unit constant mode: lane output is set to a constant (0x0) toggle mode: lane output is toggling between 0x0 and 0x1 PRBS mode: lane output is the PRSB generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_Ctrl register) not used defines lane polarity: lane polarity is normal lane polarity is inverted defines lane clock polarity: lane clock provided to the serializer is active on positive edge lane clock provided to the serializer is active on negative edge lane power-down control: lane is operational lane is in Power-down mode
0
ADC1213D_SER
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NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
Table 52. ADCA_0_Ctrl (address 0890h) ...continued Default values are highlighted. Bit 3 to 1 0 Symbol ADC_PD R/W 0 1 Table 53. ADCB_0_ctrl (address 0891h) Default values are highlighted. Bit 7 to 6 5 to 4 Symbol ADC_MODE[1:0] Access R/W 00 (reset) 01 10 11 3 to 1 0 ADC_PD R/W 0 1 000 Value 00 Description not used defines input type of JESD204A unit ADC output is connected to the JESD204A input not used JESD204A input is fed with a dummy constant, set to: OTR = 0 and ADC[11:0] = "100110111010" JESD204A is fed with a PRBS generator (PRBS type is defined with "PRBS_TYPE" (Ser_PRBS_ctrl register) not used ADC power-down control: ADC is operational ADC is in Power-down mode Access Value 000 Description not used ADC power-down control: ADC is operational ADC is in Power-down mode
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
12. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-7
D
B
A
terminal 1 index area
E
A
A1 c
detail X
e1 e L 15 14 1/2 e b 28 29 e v w CAB C y1 C
C y
Eh 1/2 e
e2
1 terminal 1 index area 56 Dh 43
42 X
0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 8.1 8.0 7.9 Dh 5.95 5.80 5.65 E(1) 8.1 8.0 7.9 Eh 6.55 6.40 6.25 e 0.5
2.5 scale e1 6.5 e2 6.5
5 mm
L 0.5 0.4 0.3
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT684-7 References IEC --JEDEC MO-220 JEITA --European projection
sot684-7_po
Issue date 08-11-19 09-03-04
Fig 24. Package outline SOT684-7 (HVQFN56)
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
13. Abbreviations
Table 54. Acronym ADC DCS ESD IF IMD LSB LVCMOS LVPECL MSB OTR PRBS SFDR SNR SPI TX Abbreviations Description Analog-to-Digital Converter Duty Cycle Stabilizer ElectroStatic Discharge Intermediate Frequency InterModulation Distortion Least Significant Bit Low Voltage Complementary Metal Oxide Semiconductor Low-Voltage Positive Emitter-Coupled Logic Most Significant Bit OuT-of-Range Pseudo-Random Binary Sequence Spurious-Free Dynamic Range Signal-to-Noise Ratio Serial Peripheral Interface Transmitter
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
14. Revision history
Table 55. Revision history Release date Data sheet status 20110209 Product data sheet Change notice Supersedes ADC1213D_SER v.5 Document ID ADC1213D_SER v.6 Modifications:
* * * * *
Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Table 29 "JESD204A configuration table" added to Section 11.6.4. All tables in Section 11.6.2 have been updated. Section 13 "Abbreviations" added to the data sheet. Preliminary data sheet Objective data sheet Objective data sheet Objective data sheet Objective data sheet ADC1213D_SER v.4 ADC1213D065_080_105_125 v.3 ADC1213D065_080_105_125 v.2 ADC1213D065_080_105_125 v.1 -
ADC1213D_SER v.5 ADC1213D_SER v.4 ADC1213D065_080_105_125 v.3 ADC1213D065_080_105_125 v.2 ADC1213D065_080_105_125 v.1
20100423 20100412 20090617 20090604 20090528
ADC1213D_SER
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2011. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
ADC1213D_SER
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Product data sheet
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.2 Clock and digital output timing . . . . . . . . . . . . 11 10.3 Serial output timing . . . . . . . . . . . . . . . . . . . . . 12 10.4 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11 Application information. . . . . . . . . . . . . . . . . . 13 11.1 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13 11.1.1 Input stage description . . . . . . . . . . . . . . . . . . 13 11.1.2 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 14 11.1.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2 System reference and power management . . 16 11.2.1 Internal/external reference . . . . . . . . . . . . . . . 16 11.2.2 Programmable full-scale . . . . . . . . . . . . . . . . . 17 11.2.3 Common-mode output voltage (VO(cm)) . . . . . 17 11.2.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11.3.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 19 11.3.3 Clock input divider . . . . . . . . . . . . . . . . . . . . . 20 11.3.4 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20 11.4 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.4.1 Serial output equivalent circuit . . . . . . . . . . . . 20 11.5 JESD204A serializer. . . . . . . . . . . . . . . . . . . . 21 11.5.1 Digital JESD204A formatter . . . . . . . . . . . . . . 21 11.5.2 ADC core output codes versus input voltage . 22 11.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . 23 11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 23 11.6.2 Channel control . . . . . . . . . . . . . . . . . . . . . . . 24 11.6.3 Register description . . . . . . . . . . . . . . . . . . . . 27 11.6.3.1 ADC control register . . . . . . . . . . . . . . . . . . . . 27 11.6.4 JESD204A digital control registers . . . . . . . . . 29 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39 15 15.1 15.2 15.3 15.4 16 17 Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 41 41 42
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2011.
All rights reserved.
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